1. Technical Field
The present invention relates to a semiconductor integrated circuit, in particular, to an apparatus and method of generating a clock signal of a semiconductor memory.
2. Related Art
Referring to FIG. 1, a conventional apparatus for generating a clock signal of a semiconductor memory includes a first shifter 10 that outputs shifting signals P0 to P3 using a plurality of periodic signals C0 to C3 whose phases are different from each other, a second shifter 20 that outputs multiplexing control signals M0 to M3 using an inverted clock signal ICLKB, a multiplexer 30 that selects and outputs one of the shifting signals P0 to P3 on the basis of the multiplexing control signals M0 to M3, and a driver 40 that drives a clock signal ICLK and the inverted clock signal ICLKB on the basis of the output of the multiplexer 30.
The operation of the apparatus for generating a clock signal of a semiconductor memory according to the related art will be described with reference to FIG. 2.
The periodic signals C0 to C3 having a pulse width of 2tck are sequentially input at predetermined phase differences. In this case, phase differences of the periodic signals C1 to C3 with respect to the periodic signal C0 are 90°, 180°, and 270°, respectively.
After the outputs of the first shifter 10 are set by a first reset signal RESET such that the shifting signal P0 is high, and the other shifting signals P1 to P3 are low, the first shifter 10 outputs the shifting signals P0 to P3 having a pulse width of 4tck on the basis of the periodic signals C0 to C3 by the time when the first reset signal RESET is disabled.
Further, after the outputs of the second shifter 20 are set by the first reset signal RESET such that the multiplexing control signal M0 is high, and the other multiplexing control signals M1 to M3 are low, the second shifter 20 outputs the multiplexing control signals M0 to M3 on the basis of the signal ICLKB by the time when the first reset signal RESET is disabled.
Thereafter, the multiplexer 30 selects corresponding shifting signals P0 to P3 when the multiplexing control signals M0 to M3 are high and outputs the clock signal ICLK through the driver 40.
That is, the shifting signal P0 is output as the clock signal ICLK during a period when the multiplexing control signal M0 is high. The shifting signal P3 is output as the clock signal ICLK during a period when the multiplexing control signal M3 is high. The shifting signal P2 is output as the clock signal ICLK during a period when the multiplexing control signal M2 is high. The shifting signal P1 is output as the clock signal ICLK during a period when the multiplexing control signal M1 is high.
As shown in FIG. 2, the pulse widths of the shifting signals P0 to P3 are 4tck, while the phase difference between the shifting signals P0 and P3, the shifting signals P3 and P2, the shifting signals P2 and P1, and the shifting signals P1 and P0 is 5tck, respectively.
However, according to the related art, a high duty cycle of the clock signal ICLK is 4tck (approximately 44%) and a low duty cycle thereof is 5tck (approximately 56%) so that the duty cycle ratio is 44:56. Therefore the duty rate of the clock signal ICLK is not uniform. As a result, since the operational margin of the structure that uses this clock signal only influences the low duty cycle side, the stability is lowered.